Parallel Read Functional Unit for Microprocessors
US Patent No: US 8,943,297 B2
Issued: January 27, 2015
USPTO Patent PDF | Google Patents
Security Area: Cryptography & AI Acceleration
Abstract
A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, a plurality of memory tables, a combinational logic circuit, and a decoder. Each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. The combinational logic circuit receives lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.
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The present invention relates to a functional unit for a microprocessor, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of Software applications, such as cryptography. The functional unit includes first and second Source registers for receiving first and second data items to be processed by the functional unit; a first bank of memory tables in connected in parallel to the first source register, each of the first bank of memory tables indexed by a first index comprising a first portion of the first data item received by the first Source register, the index pointing to a first lookup result in a respective one of the first bank of memory tables; a second bank of memory tables in connected in parallel to the first Source register, each of the second bank of memory tables indexed by a second index comprising a second portion of the first data item received by the first source register, the index pointing to a second lookup result in a respective one of the second bank of memory tables; a combinational logic circuit second source register, the combinational logic circuit receiving the lookup results from the first and second banks and processing the lookup results and the second data item in the second source register to produce a result data item; and a decoder circuit in communication with the combinational logic circuit, the decoder circuit extracting an operational code from an instruction Supplied to the functional unit, decoding the operational code, and controlling the combinational logic circuit in accordance with the operational code.
Related Patent
Related patent covers variations of this invention with different claim scopes or extensions.
US 8,352,708 B2 (Issued: January 8, 2013)