Randomized and Safe (RaS) Cache Architecture

Patent Pending

Application No: US 19/339,732

Filed: September 25, 2025

Security Areas: Preventing Speculative and Traditional Cache Information Leakage Attacks

Abstract

The present disclosure provides a cache architecture comprising a cache memory having a tag storage and a data storage, a miss status holding register (MSHR) configured to track memory requests where each memory request includes a NoFill field, a safe history buffer (SHB) configured to store safe memory addresses and generate cache line fetch requests based on the stored safe memory addresses, and a cache controller configured to prevent cache fills for memory requests having the NoFill field set, send data to a processor without filling the cache memory when the NoFill field is set, and fill the cache memory with cache lines retrieved by the cache line fetch requests generated by the SHB. The cache architecture provides security against cache timing attacks by decorrelating cache fills from actual memory requests while maintaining performance through the safe history buffer mechanism.