PATENT FAMILY
Cache Memory Having Enhanced Performance and Security Features
Architectural cache designs that enhance system performance while reducing information leakage in shared processor environments.
Overview
This patent family introduces hardware-level cache architectures designed to mitigate information leakage arising from shared cache behavior.
The inventions address risks associated with cache timing, access patterns, and resource contention in multi-core and multi-process systems.
Patents in This Family
US 8,549,208 B2 | Issued: October 1, 2013
Foundational architectural techniques for reducing side-channel observability in shared cache systems.
US 9,110,816 B2 | Issued: August 18, 2015
Expanded claim coverage addressing additional cache behavior controls in shared processor environments.
US 9,864,703 B2 | Issued: January 9, 2018
Refinements and variations extending architectural protection across shared-memory implementations.
Core Architectural Coverage
Structural cache organization techniques for shared environments
Architectural governance of shared cache resource behavior
Controls spanning privilege and process boundaries
Management of cache interactions across multi-core systems
Security integration designed to preserve baseline processor performance
Claim Scope Across the Family
Foundational architectural cache security framework
Extensions covering variations in shared-cache implementations
Protection spanning multi-core and multi-process contexts
Structural control mechanisms spanning shared-cache architectural implementations
Potential Applications
Multi-core processors
Virtualized and multi-tenant systems
Security-sensitive workloads
Environments exposed to cache side-channel risk
Licensing & Collaboration
This patent family is available for licensing and strategic collaboration.