The present invention relates to a cache memory having enhanced performance and security features. The cache memory includes a data array storing a plurality of data lines, a tag array storing a plurality of tags corresponding to the plurality of data lines, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data lines, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired by cache replacement algorithms disclosed herein. If a line number register with a matching value for the index bits and context identifier exists, a corresponding tag element from the cache tag memory is accessed and compared to the tag bits also in the address provided to the cache memory. At the same time, a corresponding data line from the cache data memory is accessed. If the tag element matches the tag bits in the address provided to the tag memory, then the corresponding data line accessed from the data array is transmitted to a processor in communication with the cache that requested a data element contained in the data line, for subsequent use by the processor. If both a matching line number register and a matching tag element are not found, the present invention also provides a method and a computer-readable medium for replacing data in a faster and smaller cache memory, with data from a larger and slower memory. A random line in the faster and smaller cache memory can be replaced with a data line from the larger and slower memory. Under other conditions, a random line in the cache can be evicted without replacing it with a data line from the larger and slower memory. User-defined and/or vendor-defined replacement procedures can also be utilized to replace data lines in the cache memory. A circuit implementation for an address decoder that is an embodiment of the present invention is also described herein.