PATENT FAMILY
System and Method for Processor-Based Security
Architectural techniques embedding security controls directly within processor execution environments to protect code and data at the hardware level.
Overview
This patent family introduces processor-level security mechanisms that integrate protection directly into the execution architecture of modern computing systems.
Rather than relying solely on external security layers, these inventions embed enforcement controls within processor operation, enabling architectural protection of execution state, memory interactions, and privilege transitions.
Patents in This Family
US 8,738,932 B2 | Issued: May 27, 2014
Introduces processor-integrated mechanisms for enforcing security policies during execution.
US 9,784,260 B2 | Issued: October 10, 2017
Extends architectural enforcement controls across broader processor interaction scenarios.
US 9,989,043 B2 | Issued: June 5, 2018
Refines and expands processor-level protection techniques spanning execution and memory contexts.
Core Architectural Coverage
Processor-integrated enforcement mechanisms
Architectural protection of execution state
Controls spanning privilege and execution boundaries
Hardware-level security independent of external software controls
Integration within processor execution pipelines and control logic
Claim Scope Across the Family
Foundational processor-based security framework
Extensions covering varied execution and memory scenarios
Architectural enforcement embedded in processor design
Layered claim coverage across multiple issued patents
Potential Applications
Secure processor and system-on-chip designs
Trusted execution environments
Multi-user and multi-process computing systems
Security-sensitive and confidentiality-focused workloads
Licensing & Collaboration
This patent family is available for licensing and strategic collaboration.