PATENT FAMILY
Randomized and Safe (RaS) Cache Architecture
An integrated cache architecture combining structural safeguards and controlled randomization to mitigate information leakage in modern processor environments.
Overview
The Randomized and Safe (RaS) Cache Architecture introduces a unified cache design framework that combines structural controls with randomized behavior to reduce observability of sensitive memory access patterns.
Unlike approaches focused solely on structural governance or isolated randomization techniques, this architecture integrates safety mechanisms directly into cache behavior, addressing leakage risks arising from shared memory use and speculative execution interactions.
Patent in This Family
Application No. 19/339,732 | Filed: September 25, 2025
Introduces an integrated cache architecture combining structural safeguards and controlled randomness to reduce deterministic leakage pathways.
Core Architectural Coverage
Integrated structural and randomized cache management
Architectural constraints on shared cache behavior
Controlled non-determinism in cache interactions
Mitigation of leakage from speculative execution effects
Compatibility with multi-core and shared-memory systems
Claim Scope Across the Family
The application provides claim coverage addressing:
Unified cache architecture combining structural safeguards and controlled randomization
Randomization embedded within structural cache controls
Architectural reduction of deterministic memory exposure
Protection spanning shared, speculative, and multi-tenant contexts
Potential Applications
High-performance processors employing speculative execution
Multi-core and shared-cache systems
Virtualized and multi-tenant computing environments
Security-sensitive and confidentiality-focused workloads
Licensing & Collaboration
This patent is available for licensing and strategic collaboration.