Secure Caches and Cache Side-Channel Attacks
Architectural techniques for securing shared cache memory systems against side-channel leakage while preserving performance in modern processors.
Security Challenge Overview
Modern processors rely heavily on shared cache memory to improve performance and efficiency across computing environments. However, shared cache structures can unintentionally expose sensitive information through observable timing differences, access patterns, and resource contention effects.
These microarchitectural side channels may allow attackers to infer confidential data across security boundaries without directly accessing protected memory.
Key challenges include:
Information leakage through shared cache timing behavior
Difficulty maintaining both security and performance in shared cache architectures
Sharing caches across context switches
Cross-process and cross-core side-channel exposure
As processor architectures continue to scale in complexity and parallelism, mitigating cache-based side channels becomes increasingly important for secure system design.
CoreSecure’s Architectural Approach
CoreSecure Technologies’ cache security patents introduce architectural techniques designed to reduce information leakage arising from shared cache behavior. This includes sharing across context switches, not just simultaneous sharing of caches. These approaches focus on modifying cache management mechanisms and memory interaction patterns in ways that limit the observability of sensitive data while maintaining efficient processor operation.
The inventions include both structural cache control mechanisms and randomized cache management strategies that reduce deterministic access patterns commonly exploited in side-channel attacks.
Key Technical Capabilities
Architectural techniques for reducing cache side-channel leakage
Structural controls over shared cache behavior
Randomized cache fill and management strategies
Performance-aware mitigation of cache timing exposure
Compatibility with modern multi-core processor architectures
Patent Portfolio: Cache Security & Side-Channel Mitigation
The following patents represent CoreSecure Technologies’ intellectual property related to architectural mitigation of cache-based side-channel risks. Each patent links to a dedicated patent page containing the abstract, links to Google Patents and the USPTO, and references to related patents within the same family.
Cache Memory Having Enhanced Performance and Security Features
US 8,549,208 B2 | Issued: October 1, 2013
US 9,110,816 B2 | Issued: August 18, 2015
US 9,864,703 B2 | Issued: January 9, 2018
Systems and Methods for Random Fill Caching and Prefetching for Secure Cache Memories
US 10,956,617 B2 | Issued: March 23, 2021
US 12,079,127 B2 | Issued: September 3, 2024
Patent Pending Application No. 18/792,903 | Filed: August 2, 2024
Potential Application Areas
Shared-memory architectures
Cloud and multi-tenant computing systems
Security-sensitive and confidentiality-focused workloads
Processor designs exposed to microarchitectural side-channel risks
High-performance computing environments requiring secure cache management
Secure processors and trusted execution environments (TEEs)
High-performance and privacy-sensitive workloads
Environments exposed to cache side-channel risk
Multi-core processors with shared cache hierarchies
Systems exposed to cache timing and access-pattern risks
Multi-core systems
Licensing & Collaboration
CoreSecure Technologies’ cache security patents are available for licensing and strategic collaboration, supporting secure processor architectures and side-channel–resilient computing systems.